Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures-Reference-Cited by-同舟云学术

Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures

Published:2005-09 Issue:9-11 Volume:45 Page:1443-1448
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Roy Arijit,Tan Cher Ming,Kumar Rakesh,Chen Xian Tong

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference20 articles.

1. Investigation of via-dominated multi-modal electromigration failure distributions in dual damascene Cu interconnects with a discussion of the statistical implications;Gill;IEEE Proc Relia Phys Symp,2002

2. Statistical study for electromigration reliability in dual-damascene Cu interconnects;Lee;IEEE Trans Device and Materials Reliability,2004

3. Mechanical stress measurement in damascene copper interconnects and influence on electromigration parameters;Reimbold;IEEE Proc IEDM,2002

4. Cher Ming Tan, Arijit Roy, Vairagar AV, Ahila Krishnamoorthy, Mhaisalkar SG. Current Crowding Effect on Copper Dual Damascene Via Bottom Failure for ULSI Applications. Accepted for publication in IEEE Trans. Device and Materials Reliability.

5. Temperature-dependent inelastic response of passivated copper films: Experiments, analyses, and implications;Shen;J Vacuum Sci and Technol B,2003

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 3D Electromigration Modelling for VLSI;2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT);2022-10-25

2. Experimenting and modeling of catastrophic failure in electromigration-induced resistance degradation for deep submicron dual-damascene copper interconnects;Solid-State Electronics;2018-10

3. Void control during plating process and thermal annealing of through-mask electroplated copper interconnects;Microelectronics Reliability;2014-04

4. Rapid ULSI Interconnect Reliability Analysis Using Neural Networks;IEEE Transactions on Device and Materials Reliability;2014-03

5. Interconnect EM Reliability Modeling at Circuit Layout Level;Electromigration Modeling at Circuit Layout Level;2013