Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs-Reference-Cited by-同舟云学术

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

Published:2017-11 Issue: Volume:78 Page:85-92
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Villalta Igor,Bidarte Unai,Gomez-Cornejo Julen,Lázaro Jesús,Astarloa Armando

Funder

Ministerio de Economı́a y Competitividad

Department of Education, Linguistic Policy and Culture

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference19 articles.

1. Virtex-5 SEU critical bit information extending the capability of the Virtex-5 SEU controller;Chapman,2010

2. Characterization of single bit and multiple cell soft error events in planar and FinFET SRAMs;Fang;IEEE Trans. Device Mater. Reliab.,2016

3. Multi-cell soft errors at advanced technology nodes;Bhuva;IEEE Trans. Nucl. Sci.,2015

4. Radiation-induced multi-bit upsets in SRAM-based FPGAs;Quinn;IEEE Trans. Nucl. Sci.,2005

5. Static proton and heavy ion testing of the xilinx virtex-5 device;Quinn,2007

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