Consideration of temperature and current stress testing on flip chip solder interconnects

Author:

Yeo Alfred,Ebersberger Bernd,Lee Charles

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. Flip chip solder joint reliability analysis using viscoplastic and elastic–plastic-creep constitutive models;Yeo;IEEE Trans Compon Packag Technol,2006

2. SEMATECH, International Technology Roadmap for Semiconductor, Assembly and Packaging, 2006 Update and 2007 Edition. .

3. EIA/JEDEC Standard No. 33-A, Standard method for measuring and using the temperature coefficient of resistance to determine the temperature of a metallization line. Electronics Industries Association Engineering Department, October 1995.

4. Yeo A, Wong FL, Lee C. Development of novel joint resistance modeling technique for flip chip interconnection systems. In: Proceedings of 31st IEMT, Putrajaya, Malaysia, November 2006. p. 115–9.

5. Geometrical effect of bump resistance for flip-chip solder joints: finite-element modeling and experimental results;Liang;J Electron Mater,2006

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2. Effect of Cu solubility on electromigration in Sn(Cu) micro joint;Journal of Applied Physics;2017-09-07

3. Numerical simulations of migration and coalescence behavior of microvoids driven by diffusion and electric field in solder interconnects;Microelectronics Reliability;2017-04

4. Improved strength of boron-doped Sn-1.0Ag-0.5Cu solder joints under aging conditions;Intermetallics;2012-01

5. Sn-Rich Phase Coarsening in Sn-Ag-Cu Solder Joint during Moderate Current Stressing;Advanced Materials Research;2011-06

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