Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs-Reference-Cited by-同舟云学术

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Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs

Published:2013-09 Issue:9-11 Volume:53 Page:1351-1354
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Lee Seonhaeng,Kim Cheolgyu,Kim Hyeokjin,Kim Gang-Jun,Seo Ji-Hoon,Son Donghee,Kang Bongkoo

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference9 articles.

1. Thermodynamic stability of high-K dielectric metal oxides ZrO2 and HfO2 in contact with Si and SiO2

2. Application of HfSiON as a gate dielectric material

3. High dielectric constant gate oxides for metal oxide Si transistors

4. Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

5. Bias Temperature Instability Characteristics of n- and p-Type Field Effect Transistors Using HfO[sub 2] Gate Dielectrics and Metal Gate

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