Author:
Abdul Wahab Y.,Soin N.,Hatta S.W.M.
Funder
University Malaya High Impact Research
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference17 articles.
1. Mistry K, Allen C, Auth C, Beattie B, Bergstrom D, Bost M et al. A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. In: Int electron dev meet tech dig; 2007. p. 247–50.
2. ITRS; 2008 .
3. Taur Y, Wann CH, Frank DJ. 25nm CMOS design considerations. In: IEDM technical digest; 1998. p. 789–92.
4. Material and process limits in silicon VLSI technology;Plummer;Proc IEEE,2001
5. NBTI degradation effect on advanced-process 45nm high-k PMOSFETs with geometric and process variations;Hatta;Microelectron Reliab,2010
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献