Some practical considerations for effective and efficient wafer-level reliability control

Author:

Tseng Summer F.C.,Chien Wei-Ting Kary,Gong Excimer,Wang Willings,Cai Bing-Chu

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference12 articles.

1. Practical building-in reliability (BIR) approaches for semiconductor manufacturing;Kary Chien;IEEE Trans. Reliab.,2002

2. Kary Chien WT, Chiang S, Tseng SFC, Huang CHJ, Yang K, Wang W, et al. Practical WLRC methodology and applications in a wafer foundry. In: International Reliability Physics Symposium, April 2003, Dallas, TX, USA

3. Noguchi K, Matsumoto A, Oda N. A model for evaluating cumulative oxide damage from multiple plasma processes. In: IEEE IRPS 2000. p. 364–9

4. EIA/JEDEC JESD61: isothermal electromigration test procedure

5. EIA/JEDEC JESD87: standard test structures for reliability assessment of Al–Cu metallization with barrier layers

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1. Fast wafer level reliability monitoring as a tool to achieve automotive quality for a wafer process;Microelectronics Reliability;2016-09

2. THE TEST-TO-TARGET METHODOLOGIES FOR THE RISK ASSESSMENT OF SEMICONDUCTOR RELIABILITY;International Journal of Reliability, Quality and Safety Engineering;2013-08

3. Negative Bias Temperature Stress on PFETs within fast Wafer Level Reliability Monitoring;2008 IEEE International Integrated Reliability Workshop Final Report;2008-10

4. Efficient fWLR inline monitoring of hot carrier reliability by means of one simple, comprehensive parameter;2005 IEEE International Integrated Reliability Workshop

5. Procedure for quantitative fWLR monitoring of gate dielectric reliability;IEEE International Integrated Reliability Workshop Final Report, 2004

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