Author:
O'Connell Barry,Chaparala Prasad,Mehrotra Bhola
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference5 articles.
1. Scaling limitations of gate oxide in P+ polysilicon gate MOS structures for sub-quarter micron CMOS devices;Uwasawa;IEDM Tech. Digest,1993
2. Impact of boron penetration at P+-poly/gate oxide interface on DSM device reliability for dual-gate CMOS technologies;Hao;IEEE Electron Dev. Lett.,1997
3. Alavi M, Jacobs S, Ahmed S, Chern CH, McGregor P. Effect of MOS device scaling on process induced gate charging. In: 2nd Intl Symp on Plasma Process Induced Damage, 1997. p. 7–10
4. Plasma induced damage;Viswanathan;Microelectron. Eng.,1999
5. A model for evaluating oxide damage from multiple plasma processes;Noguchi;IRPS,2000