A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies-Reference-Cited by-同舟云学术

A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies

Published:2005-02 Issue:2 Volume:45 Page:201-210
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Smith Jeremy C.,Boselli Gianluca

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference11 articles.

1. ESD design methodology;Merrill;EOS/ESD symp. proc.,1993

2. Sub-micron chip ESD protection schemes which avoid avalanching junctions;Worley;EOS/ESD Symp. Proc.,1995

3. Stacked PMOS clamps for high voltage power supply protection;Maloney;EOS/ESD Symp. Proc.,1999

4. Takeda F, Miller J. Patent application filed with USPTO. April 2000

5. Modular, portable and easily simulated ESD protection networks for advanced CMOS technologies;Torres;EOS/ESD Symp. Proc.,2001

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