1. A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices;Kelly,1995
2. A Sample Preparation Methodology to Reduce Sample Edge Unevenness and Improve Efficiency in Delayering the 20-nm Node IC Chips;Feng,2015
3. Passive Voltage Contrast Technique for Rapid In-line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology;Liang,1998
4. Comparison of Active and Passive Voltage Contrast for Failure Localization;Rosenkranz,2007
5. High Resolution Electron Beam Induced Resistance Change for Fault Isolation with 100 nm2 Localization;Buchea,2015