Failure analysis on 14 nm FinFET devices with ESD CDM failure

Author:

Shaalini C.,Tan P.K.,Zhao Y.Z.,Liu B.H.,Ma Y.Z.,Quah A.,Pan Y.L.,Tan H.,Mai Z.H.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference6 articles.

1. A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices;Kelly,1995

2. A Sample Preparation Methodology to Reduce Sample Edge Unevenness and Improve Efficiency in Delayering the 20-nm Node IC Chips;Feng,2015

3. Passive Voltage Contrast Technique for Rapid In-line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology;Liang,1998

4. Comparison of Active and Passive Voltage Contrast for Failure Localization;Rosenkranz,2007

5. High Resolution Electron Beam Induced Resistance Change for Fault Isolation with 100 nm2 Localization;Buchea,2015

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1. Metal Migration Induced Breakdown from Gate Contact in Bulk FinFET Devices;2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2021-09-15

2. Internal-Distributed CDM ESD Protection;2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2021-04-08

3. Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network;IEEE Journal of the Electron Devices Society;2021

4. Complex Integrated Circuits ESD Damage Diagnosis Technology and Application;2020 21st International Conference on Electronic Packaging Technology (ICEPT);2020-08

5. Misconception with Pad-Based CDM ESD Protection;2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2020-04

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