Improving ESD protection of 5 V NMOSFET large array device in 0.4 μm BCD process

Author:

Huang Shao-Chang,Chen Hung-WeiORCID,Yang Jen-Hang,Chang Mi-Chang

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference26 articles.

1. Self-protection capability of power arrays;LaFonteese,2009

2. NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13 μm CMOS technology;Salman;IEEE Trans. Device Mater. Reliab.,2002

3. ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-μm CMOS technology;Salman;IEEE Trans. Device Mater. Reliab.,2003

4. A new principle for a self-protecting power transistor array design;Vashchenko,2006

5. Improving the ESD self-protection capability of integrated power NLDMOS arrays;Vashchenko,2010

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1. Large array device characteristics improvements;Microelectronics Reliability;2021-10

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