Layout-based mitigation of single-event transient for monolithic 3D CMOS integrated circuits-Reference-Cited by-同舟云学术

Layout-based mitigation of single-event transient for monolithic 3D CMOS integrated circuits

Published:2021-11 Issue: Volume:126 Page:114210
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Zhang Junjun,Liu Fanyu,Li Bo,Huang Yang,Yang Can,Wang Guoqing,Chen Siyuan,Cheng Jinxing,Wang Qingbo,Yu Ai,Luo Jiajun

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit;Andrieu;Int. Conf. IC Des. Technol.,2018

2. Semicond. Ind. Assoc., San Jose, CA, USA,2020

3. Heterogeneous Integration Roadmap (HIR): Co-design Challenges and Perspectives;Aida,2019

4. The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process;Ahlbin;IEEE Trans. Nucl. Sci.,2010

5. New insights into single event transient propagation in chains of inverters–evidence for propagation-induced pulse broadening;Ferlet;IEEE Trans. Nucl. Sci.,2007

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1. An integrated electrocircuit configuration majorization approach based on boundary constraint and mimetic backouting mechanism;2023 3rd International Conference on Electrical Engineering and Control Science (IC2ECS);2023-12-29

2. Single Event Induced Crosstalk of Monolithic 3D Circuits Based on a 22 nm FD-SOI Technology;2022 IEEE International Reliability Physics Symposium (IRPS);2022-03