Monitor Units Assisted LDPC Decoding Algorithm based on Page BER Variation of 3D NAND Flash Memory-Reference-Cited by-同舟云学术

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Monitor Units Assisted LDPC Decoding Algorithm based on Page BER Variation of 3D NAND Flash Memory

Published:2023-08 Issue: Volume:147 Page:115034
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Zhang Bo,Wang Qi,Wang Xianliang,Yu Xiaolei,Li Qianhui,He Jing,Huo Zongliang,Ye Tianchun

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference27 articles.

1. 3-D NAND technology achievements and future scaling perspectives;Goda;IEEE Trans. Electron Devices,2020

2. N. Shibata, K. Kanda, T. Hisada, Isobe, M. Sato, Shimizu, A 19nm 112.8mm2 64Gb Multi-Level Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface, in: Digest of Technical Papers of the Solid State Circuits Conference, 2012.

3. H. Maejima, K. Kanda, S. Fujimura, T. Takagiwa, H. Nakamura, A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology, in: 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.

4. N. Shibata, K. Kanda, T. Shimizu, J. Nakai, H. Nakamura, 13.1 A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology, in: 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019.

5. J. Kim, D.H. Lee, W. Sung, Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND Flash memory error correction, in: Communications (ICC), 2012 IEEE International Conference on, 2012.

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