An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies

Author:

Alorda Bartomeu,Carmona Cristian,Torrens Gabriel,Bota Sebastia

Funder

Spanish Ministry of Science and Innovation

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. CMOS SRAM Circuit Design and Parametric Test in Nano-scaled Technologies;Pavlov,2008

2. Analysing static and dynamic write margin for nanometers SRAMs;Wang,2008

3. Probability calculation of read failures in nano-scaled SRAM cells under process variations;Aghababa;Microelectron. Reliab.,2012

4. A process-variation-tolerant dual power supply SRAM with 0.179um2 cell in 40nm CMOS using level-programmable wordline driver;Hirabayashi,2009

5. Improved evaluation method for the SRAM cell write margin by word line voltage acceleration;Makino;Circuits and Systems,2012

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. SRAM-cells Reproducibility Metrics for Physical Unclonable Function Applications;2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS);2022-11-16

2. 6T CMOS SRAM Stability in Nanoelectronic Era: From Metrics to Built-in Monitoring;Complementary Metal Oxide Semiconductor;2018-08-01

3. Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift;2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS);2017-04

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