Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology

Author:

Park Kyungbae,Lim ChulseungORCID,Yun DonghyukORCID,Baeg Sanghyeon

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference27 articles.

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3. RAIDR: retention-aware intelligent DRAM refresh;Liu,2012

4. DDR3 SDRAM Specification;JEDEC,2012

5. Memory Systems: Cache, DRAM, Disk;Jacob,2010

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2. An Experimental Analysis of RowHammer in HBM2 DRAM Chips;2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S);2023-06

3. Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

4. Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04

5. Estimation of the Trap Energy Characteristics of Row Hammer-Affected Cells in Gamma-Irradiated DDR4 DRAM;IEEE Transactions on Nuclear Science;2022-03

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