Panel level IC-package technology development-Reference-Cited by-同舟云学术

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Panel level IC-package technology development

Published:2022-09 Issue: Volume:136 Page:114657
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Fang Jen-Kuang,Fong Cher-Min,Lu Wen-Long,Yang Peng

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference35 articles.

1. Warpage and thermal characterization of fan-out wafer-level packaging;Lau;IEEE Trans. Compon. Packag. Manuf. Technol.,2017

2. Design and optimization of thermo-mechanical reliability in wafer level packaging;Fan;Microelectron. Reliab.,2010

3. 3D LED and IC wafer level packaging;Lau;Microelectron. Int.,2010

4. Development of package-on-package using embedded wafer-level package approach;Chong;IEEE Trans. Compon. Packag. Manuf. Technol.,2013

5. 3-D structure design and reliability analysis of wafer level package with stress buffer mechanism;Lee;IEEE Trans. Compon. Packag. Manuf. Technol.,2007

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