Hardware Design and Realization for Iteratively Decodable Codes-Reference-Cited by-同舟云学术

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Hardware Design and Realization for Iteratively Decodable Codes

Published:2014 Issue: Volume: Page:583-651
ISSN:
Container-title:Academic Press Library in Mobile and Wireless Communications
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Author:

Boutillon Emmanuel,Masera Guido

Publisher

Elsevier

Reference136 articles.

1. Towards an optimal parallel decoding of turbo codes;Tousch,2006

2. Terminating the trellis of turbo-codes in the same state;Barbulescu;Electron. Lett.,1995

3. A 690-mw 1-gb/s 1024-b, rate-1/2 low-density parity-check code decoder;Blanksby;IEEE J. Solid-State Circuits,2002

4. Implementation of a flexible LDPC decoder;Masera;IEEE Trans. Circuits Syst. II: Express Briefs,2007

5. A network-on-chip-based turbo/LDPC decoder architecture;Condo,2012

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes;Quantum;2024-05-02

2. Layered Decoding of Quantum LDPC Codes;2023 12th International Symposium on Topics in Coding (ISTC);2023-09-04

3. Stabilizer Inactivation for Message-Passing Decoding of Quantum LDPC Codes;2022 IEEE Information Theory Workshop (ITW);2022-11-01

4. Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-03

5. Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units;2016 Euromicro Conference on Digital System Design (DSD);2016-08

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