Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units

Author:

Nguyen-Ly Thien T.,Gupta Tushar,Pezzin Manuel,Savin Valentin,Declercq David,Cotofana Sorin

Publisher

IEEE

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. RiF: Improving Read Performance of Modern SSDs Using an On-Die Early-Retry Engine;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

2. PiF;Proceedings of the 14th ACM Workshop on Hot Topics in Storage and File Systems;2022-06-27

3. An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder;PLOS ONE;2021-03-29

4. Generalized Very High Throughput Unrolled LDPC Layered Decoder;2020 28th Telecommunications Forum (TELFOR);2020-11-24

5. Fine-Grained Bit-Flipping Decoding for LDPC Codes;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-05

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