Logic synthesis in a nutshell-Reference-Cited by-同舟云学术

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Logic synthesis in a nutshell

Published:2009 Issue: Volume: Page:299-404
ISSN:
Container-title:Electronic Design Automation
language:
Short-container-title:

Author:

Jiang Jie-Hong (Roland),Devadas Srinivas

Publisher

Elsevier

Reference87 articles.

1. Logic Minimization Algorithms for VLSI Synthesis;Brayton,1984

2. Boolean Reasoning: The Logic of Boolean Equations;Brown,2003

3. Logic Synthesis;Devadas,1994

4. Computers and Intractability: A Guide to the Theory of NP-Completeness;Garey,1979

5. Logic Synthesis and Verification;Hassoun,2002

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2. AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. Graph for VLSI Physical Design: An Extended Methodology to Explore Design Data and Boost Design Optimization;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

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