1. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 um2 SRAM cell;Thompson,2002
2. FinFET scaling to 10 nm gate length;Yu;Technical Digest – International Electron Devices Meeting,2002
3. Fifty years of Moore's law;MacK,2011
4. Graphene and two-dimensional materials for silicon technology;Akinwande;Nature,2019
5. Promises and prospects of two-dimensional transistors;Liu;Nature,2021