1. Jason Baumgartner, Viresh Paruthi, Ambar Gadkari, Pradeep Nalla, and Sivan Rabinovich, “Formal Verification at IBM-Applications and Algorithms,” Workshop on Making Formal Verification Scalable and Useable, Chennai Mathematical Institute, 2013.
2. The Chip Design Game at the End of Moore’s Law;Colwell;Hot Chips,2013
3. Jim Kasak, Ross Weber, and Holly Stump, “Formal Verification Deployment Reveals Return on Investment,” Chip Design Magazine, http://chipdesignmag.com/display.php?articleId=3398.
4. Viresh Paruthi, “Large-Scale Application of Formal Verification: From Fiction to Fact,” Formal Methods in Computer Aided Design, 2011.
5. Vigyan Singhal, “Deploying Formal in a Simulation World,” International Conference on Computer-Aided Verification, 2011.