1. Chayut, I.: Functional verification from a manager’s perspective. Synopsys Insight, 1(2) (2006),
http://www.synopsys.com/news/pubs/insight/2006/art1_verinvidia_v1s2.html
2. Foster, H., Loh, L., Rabii, B., Singhal, V.: Guidelines for creating a formal verification testplan. In: Proc. DVCon (2006)
3. Kantrowitz, M., Noack, L.M.: I’m done simulating; now what? Verification coverage analysis and correctness checking of the DECchip 21164 Alpha microprocessor. In: Proc. Design Automation Conf. pp. 325–330 (1996)
4. Tasiran, S., Keutzer, K.: Coverage metrics for functional validation of hardware designs. IEEE Des. Test. 18(4), 36–45 (2001)
5. Hoskote, Y.V., Kam, T., Ho, P.-H., Zhao, X.: Coverage estimation for symbolic model checking. In: Proc. Design Automation Conf. pp. 300–304 (1996)