Author:
Nyssens Lucas,Rack Martin,Raskin Jean-Pierre
Reference67 articles.
1. Bangsaruntip S., Balakrishnan K., Cheng S.-L., Chang J., Brink M., Lauer I., Bruce R. L., Engelmann S. U., Pyzyna A., Cohen G. M., Gignac L. M., Breslin C. M., Newbury J. S., Klaus D. P., Majumdar A., Sleight J. W., & Guillorn M. A. (2013). Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond. In 2013 IEEE international electron devices meeting (pp. 20.2.1–20.2.4). https://doi.org/10.1109/IEDM.2013.6724667.
2. Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm;Barraud;IEEE Electron Device Letters,2012
3. Ultrawide frequency range crosstalk into standard and trap-rich high resistivity silicon substrates;Ben Ali;IEEE Transactions on Electron Devices,2011
4. Bol D., Schramme M., Moreau L., Haine T., Xu P., Frenkel C., Dekimpe R., Stas F., & Flandre D. (2019). 19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with dual-loop adaptive back-bias generator for 20μs wake-up from deep fully retentive sleep mode. In 2019 IEEE international solid- state circuits conference - (ISSCC). (pp. 322–324). https://doi.org/10.1109/ISSCC.2019.8662293.
5. Bu H. (2017). 2022 8 20 5 Nanometer transistors inching their way into chips. https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/.