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Using gate-level side channel parameters for formally analyzing vulnerabilities in integrated circuits

  • Published:2019-02 Issue: Volume:171 Page:42-66
  • ISSN:0167-6423
  • Container-title:Science of Computer Programming
  • language:en
  • Short-container-title:Science of Computer Programming

Author:

Abbassi Imran Hafeez,Khalid FaiqORCID,Hasan Osman,Kamboh Awais Mehmood

Publisher

Elsevier BV

Subject

Software

Reference54 articles.

1. Formal verification of gate-level multiple side channel parameters to detect hardware Trojans;Abbasi,2016

2. The hunt for the kill switch;Adee;IEEE Spectr.,2008

3. Trojan detection using IC fingerprinting;Agrawal,2017

4. Towards Countering the Rise of the Silicon Trojan;Anderson,2008

5. A survey on hardware Trojan detection techniques;Bhasin,2015

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1. Formal timing analysis of gate-level digital circuits using model checking;Microprocessors and Microsystems;2024-09

2. Side-Channel Attack Security Risk Assessment Model Based on Mutual Information Game;Journal of Physics: Conference Series;2024-03-01

3. Bypass Leakage Risk Assessment Based on Mutual Information Game;2023 International Conference on Computer Science and Automation Technology (CSAT);2023-10-06

4. Attacks on cryptosystems implemented via VLSI: A review;Journal of Information Security and Applications;2021-08

5. ForASec: Formal Analysis of Hardware Trojan-based Security Vulnerabilities in Sequential Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021
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