Impact of Ge proportion on advanced SiGe bulk P-MOSFET matching performances

Author:

Rahhal Lama,Bajolet Aurélie,Cros Antoine,Diouf Cheikh,Kergomard Flore,Rosa Julien,Bidal Gregory,Bianchi Raul-Andres,Ghibaudo Gérard

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference44 articles.

1. Carrier-transport-enhanced channel CMOS for improved power consumption and performance;Takagi;IEEE Trans Electron Dev,2008

2. High mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band to band tunneling leakage: experiments;Krishnamohan;IEEE Trans Electron Dev,2006

3. Harris HR et al. Band-engineered Low PMOS VT with high-K/metal gates featured in a dual channel CMOS integration scheme. VLSI Symp Tech Dig; 2007. p. 154–5.

4. Lee SH et al. Vth variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16 nm node. VLSI Symp Tech Dig; 2009. p. 74–5.

5. High-performance partially depleted SOI PFETs With in situ doped SiGe raised source/drain and implant-free extension;Khakifirooz;IEEE Electron Dev Lett,2011

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