The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack

Author:

Lee M.H.,Chen K.-J.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. Son Y-H, Lee J-W, Kang P, Kang M-G, Kim JB, Lee SH, et al. Laser-induced epitaxial growth (LEG) technology for high density 3-D STACKED memory with high productivity. In: Symp VLSI tech dig; (2007). p. 80–1.

2. Chatterjee R, Fayolle M, Leduc P, Pozder S, Jones B, Acosta E, et al. Three dimensional chip stacking using a wafer-to-wafer integration. In: IEEE international interconnect technology conference; 2007. p. 81–3.

3. Park J-H, Tada M, Kuzum D, Kapur P, Yu H-Y, Wong H-SP, et al. Low temperature (⩽380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-K/metal gate stack for monolithic 3D integration. In: Tech dig international electron device meeting (IEDM), 2008. p. 389–91.

4. Low-temperature fabrication of high-mobility poly-Si TFTs for large-area LCDs;Serikawa;IEEE Trans Electron Dev,1989

5. Kim Y, Lim C, Young CD, Matthews K, Barnett J, Foran B. et al. Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer. In: Symp VLSI tech dig; 2003. p. 167–8.

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