Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance-Reference-Cited by-同舟云学术

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Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance

Published:2004-04 Issue:4 Volume:48 Page:511-519
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Gili E.,Kunz V.D.,de Groot C.H.,Uchino T.,Ashburn P.,Donaghy D.C.,Hall S.,Wang Y.,Hemment P.L.F.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. The vertical heterojunction MOSFET;De Meyer;Thin Solid Films,1998

2. Sub 100 nm vertical MOSFET with threshold voltage adjustment;Mori;IEEE Trans. Electron Devices,2002

3. A deep submicron Si1−xGex/Si vertical PMOSFET fabricated by Ge ion implantation;Liu;IEEE Electron Device Lett.,1998

4. A high-performance five-channel NMOSFET using selective epitaxial growth and lateral solid phase epitaxy;Kumar;IEEE Electron Device Lett.,2002

5. Donaghy DC, Hall S, Kunz VD, de Groot CH, Ashburn P. Investigating 50 nm channel length vertical MOSFETs containing a dielectric pocket, in a circuit environment. Proceedings of ESSDERC 2002 2002;499–502

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1. Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node;ECS Journal of Solid State Science and Technology;2022-04-01

2. 18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications;Silicon;2021-10-05

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4. Analysis of gate engineered asymmetric junctionless double gate MOSFET for varying operating conditions;IOP Conference Series: Materials Science and Engineering;2020-06-01

5. SOI-MOSFETs;NanoScience and Technology;2016

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