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A new compact analytical model of single electron transistor for hybrid SET–MOS circuits

  • Published:2015-02 Issue: Volume:104 Page:90-95
  • ISSN:0038-1101
  • Container-title:Solid-State Electronics
  • language:en
  • Short-container-title:Solid-State Electronics

Author:

Jain Amit,Nameriakpam Basanta Singh,Sarkar Subir Kumar

Funder

UGC UPE-Phase II Project, Jadavpur University

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference25 articles.

1. Single-electron devices and their applications;Likharev;Proc IEEE,1999

2. Complementary digital logic based on the Coulomb blockade;Tucker;J Appl Phys,1992

3. Single-electron transistor logic;Chen;Appl Phys Lett,1996

4. Few electron devices: towards hybrid CMOS–SET integrated circuits;Ionescu;Proc DAC,2002

5. Novel hybrid voltage controlled ring oscillators using single electron and MOS transistors;Zhang;IEEE Trans Nanotechnol,2007

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1. CMOS Compatible Single-Gate Single Electron Transistor (SG-SET) Based Hybrid SETMOS Logic;Nanoscale Field Effect Transistors: Emerging Applications;2023-12-19

2. Design strategy and simulation of single-gate SET for novel SETMOS hybridization;Journal of Computational Electronics;2021-01-03

3. Novel Hybrid Silicon SETMOS Design for Power Efficient Room Temperature Operation;Silicon;2020-03-31

4. A Hammerstein–Wiener Model for Single-Electron Transistors;IEEE Transactions on Electron Devices;2019-02

5. Error probability independent delay analysis of single electronics circuits;International Journal of Circuit Theory and Applications;2017-08-25
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