Author:
Le Royer C.,Villalon A.,Hutin L.,Martinie S.,Nguyen P.,Barraud S.,Glowacki F.,Allain F.,Bernier N.,Cristoloveanu S.,Vinet M.
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference11 articles.
1. Impact of SOI, Si1−xGexOI and GeOI substrates on CMOS compatible tunnel FET performance;Mayer;IEDM Tech Dig,2008
2. Leonelli D, Vandooren A, Rooyackers R, Verhulst AS, De Gendt S, Heyns MM, et al. Multiple-gate tunneling field effect transistors with sub-60mV/dec subthreshold slope. In: Proc. int. conf. solid state devices and materials (SSDM); 2009. p. 767–8.
3. Low-voltage tunnel transistors for beyond CMOS logic;Seabaugh;Proc IEEE,2010
4. Dewey G, Chu-Kung B, Kotlyar R, Metz M, Mukherjee N, Radosavljevic M. III–V field effect transistors for future ultra-low power applications. In: VLSI symp. tech. dig.; 2012. p. 45–6.
5. Tomioka K, Yoshimura M, Fukui T. Steep-slope tunnel fieldeffect transistors using III–V nanowire/Si heterojunction. In: VLSI symp. tech. dig.; 2012. p. 47–8.
Cited by
12 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献