Author:
Ezawa Hirokazu,Seto Masaharu,Miyata Masahiro,Tazawa Hiroshi
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference5 articles.
1. Stencil printing process development for flip chip interconnect;Li;IEEE Trans. Electron. Packag. Manuf.,2000
2. Bump formation for flip chip and CSP by solder paste printing;Kloeser;Microelectron. Reliab.,2002
3. New screen printable polyimide for IC devices;Nishizawa;IEEE Trans. Components, Hybrids, Manuf. Technol.,1990
4. http://www.cgco.co.jp
5. Patel CS, Realff M, Merriweather S, Power C, Martin K, Meindl JD. Cost analysis of compliant wafer level package, In: Proccedings of the 50th Electronic Components and Technology Conference, 2000. p. 1634–9
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Magnetic anisotropy of ultrafine 316L stainless steel fibers;Journal of Magnetism and Magnetic Materials;2016-12
2. Mid-end Process Technologies for Advanced Packaging of LSI Devices;Journal of Photopolymer Science and Technology;2012
3. Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection;IEEE Transactions on Components and Packaging Technologies;2006-12
4. Materials and processes issues in fine pitch eutectic solder flip chip interconnection;Proceedings of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP '04)