Yield and reliability analysis of digital standard cells with resistive defects-Reference-Cited by-同舟云学术

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Yield and reliability analysis of digital standard cells with resistive defects

Published:2000-08 Issue:8-10 Volume:40 Page:1635-1640
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Huber M.,Nirschl Th.,Gstöttner J.,Heinitz M.,Zanon Th.,Maly W.,Schmitt-Landsiedel D.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference6 articles.

1. From Contamination to Defects, Faults and Yield Loss;Khare,1996

2. A defect model of reliability;Shirleyz;Tutorial Notes IRPS,1995

3. Defects, Faults and Semiconductor Device Yield;Ferris-Prabhu,1989

4. Integrated circuit yield statistics;Stapper,1993

5. ‘Resistive’ Shorts Within CMOS Gates;Hao,1991

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test;Microelectronics Reliability;2012-11

2. MALTY––A memory test structure for analysis in the early phase of the technology development;Microelectronics Reliability;2003-09

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