A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies-Reference-Cited by-同舟云学术

A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

Published:2001-03 Issue:3 Volume:41 Page:335-348
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Voldman S,Anderson W,Ashton R,Chaine M,Duvvury C,Maloney T,Worley E

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference28 articles.

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3. Voldman S, Anderson W, Ashton R, Chaine M, Duvvury C, Maloney T, Worley E. ESD technology benchmarking strategy for evaluating electrostatic discharge robustness of CMOS technologies. Integrated Reliability Workshop (IRW) Proceedings, Integrated Reliability Workshop, Lake Tahoe, Nevada, October 12–16, 1998

4. Ashton R, Voldman S, Anderson W, Chaine M, Duvvury C, Maloney T, Worley E. Characterization of ESD robustness for CMOS technology. International Conference on Microelectronic Test Structures (ICMTS) Tutorial Short Course. International Conference on Microelectronics Test Structures, Sweden, February 1999

5. Determination of threshold failure levels of semiconductor diodes and transistors due to pulsed voltages;Wunsch;IEEE Trans Nucl Sci,1968

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