Low cost bumping by stencil printing: process qualification for 200 μm pitch-Reference-Cited by-同舟云学术

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Published:2000-03 Issue:3 Volume:40 Page:497-505
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Kloeser Joachim,Heinricht Katrin,Jung Erik,Lauter Liane,Ostmann Andreas,Aschenbrenner Rolf,Reichl Herbert

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. Vardaman EJ, Goodman T. FCIP and expanding markets for flip chip. Tech-Search International Industry Report, July 1997

2. Belmonte J, Johnson A, Pernice B. Bumping wafers using stencil printing. Proceedings of the Nepcon West Conference. Anaheim, CA, 1998

3. Solder flip chips employing electroless nickel: an evaluation of reliability and cost;Stepniak;Adv Electron Packaging,1997

4. Wong K, Chi K, Rangappan A. Application of electroless Ni plating in the semi-conductor microcircuit industry. Plat and Surf Finishing 1988;70–6

5. Yamakawa K, Inaba M, Iwase N. Maskless bumping by electroless plating for high pin count, thin and low cost microcircuits. Proceedings of the ISHM. Baltimore, 1989. p. 620–6

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