Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits-Reference-Cited by-同舟云学术

Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits

Published:2004-01 Issue:1 Volume:44 Page:173-178
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Stojčev Mile K,Djordjević Goran Lj,Stanković Tatjana R

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

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5. Logic synthesis of multilevel circuits with concurrent error detection;Touba;IEEE Trans. CAD,1997

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