Author:
Kasprowicz Dominik,Pleskacz Witold A.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference11 articles.
1. Estimation of the IC layout sensitivity to spot defects;Pleskacz;Electron Technology,1999
2. Pleskacz WA, Maly W. Improved yield model for submicron domain. In: Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT’97, Paris, France, October 1997. p. 2–10
3. Blyzniuk M, Pleskacz WA, Lobur M, Kuzmicz W. Estimation of the usefulness of test vector components for detecting faults resulting from shorts in standard cells. In: Proceedings of the 7th International Conference: Mixed Design of Integrated Circuits and Systems, MIXDES 2000, Gdynia, Poland, June 2000. p. 527–32
4. Blyzniuk M, Cibakova T, Gramatova E, Kuzmicz W, Lobur M, Pleskacz WA, et al. Hierarchical defect-oriented fault simulation for digital circuits. In: Proceedings of the IEEE European Test Workshop, Cascais, Portugal, May 2000. p. 69–74
5. Blyzniuk M, Cibakova T, Gramatova E, Kuzmicz W, Lobur M, Pleskacz WA, et al. Defect oriented fault coverage of 100% stuck-at fault test sets. In: Proceedings of the 7th International Conference: Mixed Design of Integrated Circuits and Systems, MIXDES 2000, Gdynia, Poland, June 2000. p. 511–6
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