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Low-Power Testing

Published:2008 Issue: Volume: Page:307-350
ISSN:
Container-title:System-on-Chip Test Architectures
language:
Short-container-title:

Author:

Girard Patrick,Wen Xiaoqing,Touba Nur A.

Publisher

Elsevier

Reference97 articles.

1. Thermal Testing of Integrated Circuits;Altet,2002

2. Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits;Bushnell,2000

3. Design-for-Test for Digital IC's and Embedded Core Systems;Crouch,1999

4. Testing of Digital Systems;Jha,2003

5. Delay Fault Testing for VLSI Circuits;Krstic,1998

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. LoCCo-Based Scan Chain Stitching for Low-Power DFT;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-11

2. Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2016

3. A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing;Journal of Electronic Testing;2015-08

4. On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST;IEICE Transactions on Information and Systems;2014

5. A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing;IEICE Transactions on Information and Systems;2013

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