A current monitoring technique for I testing in digital integrated circuits

Author:

Matakias Sotiris,Tsiatouhas Yiorgos,Arapoyanni Angela,Haniotakis Themistoklis

Funder

European Social Fund and National Resources

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference43 articles.

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2. Models in Hardware Testing, Chapter 2;Renovell,2010

3. A. Keshavarzi, K. Roy, C.F. Hawkins, Intrinsic leakage in low power deep submicron CMOS ICs, in: Proceedings of the International Test Conference (ITC), 1997, pp. 146–155.

4. Design challenges of technology scaling;Borkar;IEEE Micro,1999

5. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies;Henzler,2007

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design, Analysis, and Testing of Low-Voltage CMOS OTA;Lecture Notes in Electrical Engineering;2018-07-31

2. Fault tolerant system based on Iddq testing;International Journal of Electronics;2018-01-10

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