Graph-based STA for asynchronous controllers-Reference-Cited by-同舟云学术

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Graph-based STA for asynchronous controllers

Published:2020-11 Issue: Volume:75 Page:91-101
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Simoglou Stavros,Xiromeritis Nikolaos,Sotiriou Christos,Sketopoulos Nikolaos

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference24 articles.

1. A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-Effective GALS Multicore Systems;Ghiribaldi,2013

2. Asynchronous sub-threshold ultra-low power processor;Diamant,2015

3. Breaking the EDA Barrier in Async Design;EE Times,2003

4. Graph-based STA for asynchronous controllers;Xiromeritis,2019

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1. RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening;2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2022-10-19

2. Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

3. Self-timed Reinforcement Learning using Tsetlin Machine;2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2021-09

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