Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design-Reference-Cited by-同舟云学术

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Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design

Published:2017-06 Issue: Volume:58 Page:167-188
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Mukherjee Priyajit,Chattopadhyay Santanu

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference36 articles.

1. Networks on Chip;Jantsch,2007

2. International Technology Roadmap for Semiconductors, Technical Report 〈http://public.itrs.net〉.

3. A global wiring paradigm for deep submicron design;Sylvester;IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.,2000

4. The future of wires;Ho;Proc. IEEE,2001

5. Designing Reliable and Efficient Networks on Chips;Murali,2009

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1. A new adaptive selection strategy for reducing latency in networks on chip;Integration;2023-03

2. Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture;Integration;2023-03

3. A Hybrid Selection Strategy Based on Traffic Analysis for Improving Performance in Networks on Chip;Journal of Sensors;2022-04-26

4. Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip;Journal of Systems Architecture;2021-06

5. SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router;IEEE Access;2021

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