Logic-level mapping of high-level faults-Reference-Cited by-同舟云学术

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Logic-level mapping of high-level faults

Published:2005-01 Issue:3 Volume:38 Page:467-490
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Fummi F.,Marconcini C.,Pravadelli G.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference21 articles.

1. Digital Systems Testings and Testable Design;Abramovici,1990

2. B-algorithm;Cho,1994

3. VHDL behavioral ATPG and fault simulation of digital systems;Chen;IEEE Trans. Aerosp. Electron. Syst.,1998

4. An RT-level fault model with high gate level correlation;Corno,2000

5. Testability analysis and ATPG on behavioral RT-level VHDL;Corno,1997

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1. Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations;2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems;2011-10

2. HIFSuite: Tools for HDL Code Conversion and Manipulation;EURASIP Journal on Embedded Systems;2010

3. Properties Incompleteness Evaluation by Functional Verification;IEEE Transactions on Computers;2007-04

4. Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM;IET Computers & Digital Techniques;2007

5. Functional Verification of Networked Embedded Systems;Sixth International Symposium on Quality of Electronic Design (ISQED'05)

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