1. VLSI Test Principles and Architectures;Wang,2006
2. K. K. Saluja and M. Karpovsky, “Testing computer hardware through data compression in space and time,” in: Proceedings of International Test Conference, 1983, pp. 83–88.
3. P. Wohl, J. A. Waicukauski, and T. W. Wiliams, “Design of compactors for signature-analyzers in built-in self-test,” in: Proceedings of International Test Conference, 2001, pp. 54-63.
4. Space compression method for built-in self-testing of VLSI circuits;Jone;Int. J. Comput. Aided VLSI Des.,1991
5. Space compression methods with output data modification;Li;IEEE Trans. Comput. -Aided Des.,1987