Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency
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Elsevier BV
Reference9 articles.
1. Built-in jitter measurement circuit with calibration techniques for a 3-GHz clock generator;Cheng;IEEE Trans. Very Large Scale Integr. Syst.,2011
2. A 6-GHz built-in jitter measurement circuit using multiphase sampler;Cheng;Transactions on Circuit and Systems II,2011
3. CMOS circuits to measure timing jitter using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation;Niitsu;IEEE J. Solid State Circ.,2012
4. An all-digital on-chip peak-to-peak jitter measurement circuit with automatic resolution calibration for high PVT-variation resilience;Chou;IEEE Transactions on Circuits and Systems I: Regular Papers,2019
5. A sub-mW on-chip period-jitter measurement circuit using automatic hidden run-time resolution calibration;Chou;IEEE J. Solid-State Circuits Letter,2020
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