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Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework

  • Published:2020-03 Issue: Volume:71 Page:56-69
  • ISSN:0167-9260
  • Container-title:Integration
  • language:en
  • Short-container-title:Integration

Author:

Garzón Esteban,De Rose Raffaele,Crupi Felice,Trojman Lionel,Finocchio Giovanni,Carpentieri Mario,Lanuzza Marco

Funder

Agenzia Spaziale Italiana

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference29 articles.

1. The promise of nanomagnetics and spintronics for future logic and universal memory;Wolf;Proc. IEEE,2010

2. A new spin on magnetic memories;Kent;Nat. Nanotechnol.,2015

3. Enabling the Internet of Things – from Integrated Circuits to Integrated Systems,2017

4. Spin-transfer torque memories: devices, circuits, and systems;Fong;Proc. IEEE,2016

5. High-density and robust STT-MRAM array through device/circuit/architecture interactions;Kwon;IEEE Trans. Nanotechnol.,2015

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