Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms-Reference-Cited by-同舟云学术

Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms

Published:2018-01 Issue: Volume:60 Page:25-38
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Singh Kunwar,Jain Aman,Mittal Aviral,Yadav Vinay,Singh Atul Anshuman,Jain Anmoll Kumar,Gupta Maneesha

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference39 articles.

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