Performance Optimization of 4-bit Absolute Value Detector Based on Structural Design

Abstract

Abstract The demand for high-speed electronics is increasing, so this paper presents a new design for a 4-bit absolute value detector, an introductory module in high-speed electronics, using the basic gate circuit except for the transmission gate. This paper introduces the logical effort theory to calculate the worst-case delay of the designed circuit, combines the designed circuit with the relevant equation of the logical effort theory to analyze the delay influencing factors of the circuit, and verifies that the designed circuit achieves the minimum delay to realize the minimum delay design of the basic module. In this paper, the circuit is divided into an absolute value output device and a numerical comparator, but the topology used is a fusion circuit of these two parts, rather than simply connecting the two parts. This study achieves a branch-free circuit while maintaining the condition of minimizing the critical path.