1. ageopt-rmt: compiler-driven variation-aware aging optimization for redundant multithreading;Knebel,2016
2. A spare link based reliable network-on-chip design;Chatterjee,2014
3. An efficient timing analysis model for 6t finfet sram using current-based method;Cui,2016
4. Joint soft-error-rate (ser) estimation for combinational logic and sequential elements;Li,2016
5. Network-on-chip: the Next Generation of System-on-chip Integration;Kundu,2014