Capture-power-aware test data compression using selective encoding

Author:

Li Jia,Liu Xiao,Zhang Yubin,Hu Yu,Li Xiaowei,Xu Qiang

Funder

National Natural Science Foundation of China

NSFC/RGC Joint Research Scheme

National Basic Research Program of China

National High-Tech Research & Development Program of China

Key Laboratory of Computer System and Architecture

China Postdoctoral Science Foundation under grant

Hong Kong SAR Research Grants Council (RGC) under the General Research Fund

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference42 articles.

1. International SEMATECH, The International Technology Roadmap for Semiconductors (ITRS): 2001 Edition, 〈http://public.itrs.net/Files/2001ITRS/Home.htm〉, 2001.

2. A. Jas, N. Touba, Test vector decompression via cyclical scan chains and its application to testing core-based designs, in: Proceedings of the IEEE International Test Conference (ITC), Washington, DC, 1998, pp. 458–464.

3. System-on-a-chip test-data compression and decompression architectures based on Golomb codes;Chandra;IEEE Transactions on Computer-Aided Design,2001

4. Reduction of SOC test data volume, scan power and testing time using alternating run-length codes;Chandra,2002

5. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes;Chandra;IEEE Transactions on Computers,2003

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