Statistical DOE–ILP based power–performance–process (P3) optimization of nano-CMOS SRAM-Reference-Cited by-同舟云学术

Statistical DOE–ILP based power–performance–process (P3) optimization of nano-CMOS SRAM

Published:2012-01 Issue:1 Volume:45 Page:33-45
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Mohanty Saraju P.,Singh Jawar,Kougianos Elias,Pradhan Dhiraj K.

Funder

NSF awards

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference36 articles.

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3. W. Zhao, Y. Cao, New generation of predictive technology model for sub-45nm design exploration, in: Proceedings of the International Symposium on Quality Electronic Design, 2006, pp. 585–590.

4. Low-leakage asymmetric-cell SRAM;Azizi;IEEE Transactions on Very Large Scale Integration Systems,2003

5. A case for asymmetric-cell cache memories;Moshovos;IEEE Transactions on Very Large Scale Integration Systems,2005

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