Low-complex processing element architecture for successive cancellation decoder

Author:

Sathees Babu Geethu,Madala Lakshmi Renuka,Gopalakrishnan Lakshminarayanan,Sellathurai Mathini

Funder

DST

EDA

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference23 articles.

1. Channel polarization: a method for constructing capacity achieving codes for symmetric binary-input memoryless channels;Arikan;IEEE Trans. Inf. Theor.,2009

2. An efficient partial sum network architecture for semi-parallel polar codes decoder implementation;Fan;IEEE Trans. Signal Process.,2014

3. A high-throughput energy efficient implementation of successive cancellation decoder;Dizdar;IEEE Trans. Circu. Syst-I: Regular papers,2016

4. A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS;Mishra,2012

5. Low-latency successive cancellation polar decoder architectures using 2-bit decoding;Yuan;IEEE Trans. Circuits Syst. I, Regular Paper,2014

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