Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

Author:

Ebrahimi Masoumeh,Daneshtalab Masoud,Liljeberg Pasi,Plosila Juha,Tenhunen Hannu

Publisher

Elsevier BV

Subject

Applied Mathematics,Computational Theory and Mathematics,Computer Networks and Communications,Theoretical Computer Science

Reference46 articles.

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2. System-on-chip beyond the nanometer wall;Magarshack,2003

3. W.J. Dally, B. Towles, Route packets, not wires: On-chip interconnection networks, in: Proceedings of the 38th Design Automation Conference, June 2001, pp. 684–689.

4. Networks on Chip;Jantsch,2003

5. Interconnection Networks: An Engineering Approach;Duato,2003

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1. Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks;Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip;2019-10-17

2. Study on logic-based routing for 3D NOCs;Proceedings of the 12th International Workshop on Network on Chip Architectures;2019-10-13

3. KBMA: A knowledge‐based multi‐objective application mapping approach for 3D NoC;IET Computers & Digital Techniques;2019-03-20

4. Interconnection Networks;Computer Communications and Networks;2018

5. Thermal management in 3d networks-on-chip using dynamic link sharing;Microprocessors and Microsystems;2017-07

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