Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging-Reference-Cited by-同舟云学术

Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging

Published:2013-12 Issue: Volume:203 Page:52-61
ISSN:0924-4247
Container-title:Sensors and Actuators A: Physical
language:en
Short-container-title:Sensors and Actuators A: Physical

Author:

Shi Shuai,Wang Xuefang,Xu Chunlin,Yuan Jiaojiao,Fang Jing,Liu Sheng

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Metals and Alloys,Surfaces, Coatings and Films,Condensed Matter Physics,Instrumentation,Electronic, Optical and Magnetic Materials

Reference25 articles.

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4. Three-dimensional integration technology based on wafer bonding with vertical buried interconnections;Koyanagi;IEEE Transactions on Electron Devices,2006

5. Three-dimensional silicon integration;Knickerbocker;IBM Journal of Research and Development,2008

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